1. Field of the Invention
Embodiments of the invention relate generally to memory systems and more specifically to an efficient line and page organization for compression status bit caching.
2. Description of the Related Art
Performance requirements are continually increasing in data processing systems, conventionally comprising one or more processor chips and attached memory devices organized as independently operating partitions. System performance is generally determined by on-chip data processing performance as well as effective bandwidth to the attached memory devices. One technique for increasing effective memory bandwidth, and therefore overall performance, is to store certain blocks of data within the attached memory in a compressed format. A plurality of both loss-less and lossy compression formats, as well as blocks not subject to any compression may coexist within attached memory. A compression status is associated with each block to specify whether the block of original data is stored uncompressed or using one of the plurality of compression formats. Each compression format advantageously reduces the number of bits needed to represent a block of original data stored in attached memory. A compression status bit set is associated with each block to encode the compression status for the block. Compression status bit sets for all compressible blocks may be stored as a compression status structure within attached memory. Sequential compression status bit sets within the compression status structure correspond to sequential blocks in the attached memory devices. Dedicated circuits coupled to a memory interface module typically perform compression and decompression operations based on compression status for a block being accessed. The memory interface module maps each physical address to one of one or more memory partitions to access a specified block of memory within the partition.
Another technique for increasing effective memory bandwidth is caching, whereby bandwidth demand is shifted from the attached memory devices to on-chip cache storage that provides low latency and high bandwidth access to data. Cache storage is typically organized as cache lines, with each complete cache line being filled or flushed in response to a respective read or write. A cache line is conventionally sized as an integral multiple of an access quantum to attached memory devices. A compression status bit cache is configured to store a plurality of compression status bit sets per cache line, thereby facilitating access to compression status bit sets for sequential physically addressed blocks in attached memory devices. Compression status stored by a given compression status bit set is used to determine compression format and therefore access size for a block of data prior to an access being initiated to the block of data.
Memory management of modern data processing systems typically implements a virtual memory access model for memory clients. Regions of contiguous virtual memory may be allocated and used by the memory clients, with access locality associated with virtual addresses. However, a contiguous range of virtual addresses may map arbitrarily to physical addresses. As such, an arbitrarily large number of compression status bit cache lines may be needed to store compression status bits associated with a given contiguous virtual address range. This can lead to cache fragmentation in the compression status bit cache and relatively inefficient use of associated cache storage, reducing overall efficiency for the processing system.
Accordingly, what is needed in the art is a technique for improving access efficiency for compression status bits in a virtual memory system.